The present invention relates to the fabrication of CMOS-based light-sensing and light-emitting devices, and in particular to layouts for the fabrication of such devices.
Conventional CMOS image sensors use of the built-in pn-junction formed by the source/drain and potential-well regions (n-type or p-type) of MOSFETs as the photo-diode. For that reason many important characteristics of the photo-diode are coupled to the design of CMOS devices. CMOS image sensors enable “active pixels”, in which one of more CMOS devices are used for the electronic amplification of the photo-generated signal. The readout process is non-destructive and consists in transferring the photo-generated charges to the gate of a MOSFET whose transconductance translates those charges into a voltage or current. The junction used as storage node must be reset before a subsequent image acquisition.
Other drawbacks of conventional CMOS image sensors include: (1) High source/drain junction capacitance tied to CMOS design, resulting in low “charge-to-voltage” conversion efficiency; (2) Crosstalk under STI, between adjacent pixels; (3) Time integration at the pixel of photo-generated signals does not favor “Time-Of-Flight” (TOF) measurements that enable 3-dimensional image sensing; (4) Conventional layouts and peripheral circuitry do not allow the aggregation of signals from several pixels to trade resolution versus signals strength or bandwidth.
In conventional CMOS image sensors the junction performing photo-detection is in the substrate bulk, cannot be run in the avalanche mode, and cannot be bandgap engineered. It has been known since the early times of semiconductor technology that indirect bandgap materials, such as silicon and germanium, can emit light when pn-junctions are operated in the avalanche mode. For a number of reasons, conventional CMOS and BiCMOS technologies have not lead to the practical use of such capability.